This application claims priority of Taiwan patent Application No. 90106689, filed on Mar. 21, 2001.
1. Field of the Invention
The invention relates to a frequency synthesizer, more particularly to a phase-locked loop frequency synthesizer.
2. Description of the Related Art
FIG. 1 illustrates a conventional phase-locked loop frequency synthesizer disclosed in U.S. Pat. No. 5,173,665, entitled xe2x80x9cPLL Frequency Synthesizer Capable of Changing an Output Frequency at a High Speedxe2x80x9d. The conventional phase-locked loop frequency synthesizer includes a reference signal generator 121, a first pulse removing circuit 131, a second pulse removing circuit 132, a phase-frequency comparator 124, a charge pump circuit 125, a loop filter 126, a voltage controlled oscillator 122, and a variable frequency divider 123.
One of the drawbacks of the conventional phase-locked loop frequency synthesizer disclosed in the aforesaid. U.S. Patent resides in that, due to the absence of a common control signal for controlling the first and second pulse removing circuits 131, 132, synchronized operation of the first and second pulse removing circuits 131, 132 cannot be ensured. In other words, the first and second pulse removing circuits 131, 132 may produce a synchronous first and second pulse removed signals when the divisors A1, A2 are changed.
Therefore, the object of the present invention is to provide a phase-locked loop frequency synthesizer that includes a pair of controllable synchronous frequency dividers controlled by a common frequency dividing control signal.
According to the present invention, a phase-locked loop frequency synthesizer comprises:
a reference signal generator for generating a reference signal with a reference frequency;
a voltage controlled oscillator for generating an output signal having an output frequency in response to a control voltage signal received thereby;
a first variable frequency divider connected to the reference signal generator for frequency dividing the reference signal on the basis of a first divisor so as to generate a divided reference signal;
a second variable frequency divider connected to the voltage controlled oscillator for frequency dividing the output signal on the basis of a second divisor so as to generate a divided output signal;
a first controllable synchronous frequency divider connected to the first variable frequency divider for frequency dividing the divided reference signal on the basis of a third divisor upon receiving a frequency dividing control signal so as to generate a first low frequency signal;
a second controllable synchronous frequency divider connected to the second variable frequency divider for frequency dividing the divided output signal on the basis of the third divisor upon receiving the frequency dividing control signal so as to generate a second low frequency signal;
a phase-frequency comparator connected to the first and second controllable synchronous frequency dividers for receiving the first and second low frequency signals therefrom, the phase-frequency comparator comparing the first and second low frequency signals and outputting an adjust signal according to a detected difference therebetween;
a control voltage generating circuit connected to the voltage controlled oscillator and the phase-frequency comparator, the control voltage generating circuit supplying the control voltage signal to the voltage controlled oscillator in response to the adjust signal;
a phase-locked detector connected to the phase-frequency comparator for outputting a phase-locked signal in response to the adjust signal; and
a switching control logic connected to the phase-locked detector, the control voltage generating circuit, the first variable frequency divider, and the first and second controllable synchronous frequency dividers, the switching control logic being operable so as to supply the frequency dividing control signal to the first and second controllable synchronous frequency dividers with reference to the divided reference signal from the first variable frequency divider upon receiving the phase-locked signal from the phase-locked detector.